Oberon RTK
Basics
About Real-time Systems
Processes
Updates
2024
2025
Description
Two Processor Cores
Start-up
Text Output and Input
Runtime Errors
Inter-core Messages
Timers and Timing
Flash Memory
Traps
Device Modules
Modules
Generic
RP2040 and RP2350
RP2040
RP2350
Kernel-v1
Kernel-v2
Pico Boards
Examples
Build and Run
Set-up
Example Programs for libv2
Example Programs for lib (v1)
Tools
Astrobe
makeuf2
pio2o
abin2uf2
abin2uf22
About
Purpose
Licences
Repositories
This Site
Search
SPIdata
libv2
Data IO via SPI devices. HW-buffered, busy-waiting.
Updated: 2024-11-10
Purpose
Data IO procedures, master mode, 8 bits, MSB first for now
HW-buffered (FIFO)
Busy-waiting (blocking) while transmitting and receiving
See Also
SPIdev.mod
Example Program
SPIrtc2
Repository
SPIdata.mod